 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| User Guide -- EP9134_UG V0.2 4 Ports HDMI 1.3 Splitter EP9134 User Guide V0.2 www..com Revised: Mar. 14, 2008 Original Release Date: Aug. 27, 2007 Explore Explore reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Explore does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. Explore products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Explore product could create a situation where personal injury or death may occur. Should Buyer purchase or use Explore products for any such unintended or unauthorized application, Buyer shall indemnify and hold Explore and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Explore was negligent regarding the design or manufacture of the part. Explore Confidential Proprietary NON-DISCLOSURE AGREEMENT REQUIRED 1 User Guide -- EP9134_UG V0.2 Revision History Version Number 0.0 0.1 0.2 Revision Date Aug/27/2007 Jan/11/2008 Mar/14/2008 Author Jerry Chen Ether Lai Ether Lai Initial Version Revised Version Description of Changes Revise Register Description; Change package type; www..com 2 Explore Confidential Proprietary NON-DISCLOSURE AGREEMENT REQUIRED User Guide -- EP9134_UG V0.2 Section 1 Introduction 1.1 Overview The EP9134 is a 4-Port DVI/HDMI splitter with integrated HDCP decryption/encryption engines and is compliant with HDMI Rev 1.3b and HDCP Rev 1.2 specifications. The EP9134 receives DVI/HDMI inputs, process HDCP decryption and encryption and transmits the data to 4 DVI/HDMI ports. The chip uses an external EE to store the encrypted HDCP receiver/transmitter keys. 1.2 Features www..com * * * * * * * * * * * DVI Specification 1.0 Compliant HDMI Specification 1.3b Compliant Integrated HDCP decryption/encryption engines which are compliant with HDCP Rev 1.1 specification Encrypted HDCP keys store in external serial EE Wide Frequency Range: 25MHz - 225MHz Support 12-bit Deep Color up to 1080p Supports 1 DVI/HDMI input port and 4 DVI/HDMI output ports Supports conversion of HDMI signaling to DVI signaling Supports HDCP Repeater Cascadable to make more than 4 output ports 128-Pin HQFP (Pb-Free) 3 Explore Confidential Proprietary NON-DISCLOSURE AGREEMENT REQUIRED User Guide -- EP9134_UG V0.2 www..com 4 Explore Confidential Proprietary NON-DISCLOSURE AGREEMENT REQUIRED User Guide -- EP9134_UG V0.2 Section 2 Overview 2.1 Block Diagram Figure 2-1 Block Diagram SDA3 SCL3 IIC Slave www..com EXT_RSTb EXT_SWING Registers & Logics SDA1 SCL1 IIC Slave DVI/HDMI Receiver RX0+/RX1+/RX2+/RXC+/- HDCP Keys SDA2 SCL2 IIC Master DVI/HDMI Transmitter TX00+/TX10+/TX20+/TXC0+/- HDCP Keys HDCP Keys DVI/HDMI Transmitter DVI/HDMI Transmitter TX02+/TX12+/TX22+/TXC0+/- HDCP Keys HDCP Keys DVI/HDMI Transmitter Explore Confidential Proprietary NON-DISCLOSURE AGREEMENT REQUIRED TX03+/TX13+/TX23+/TXC1+/- TX01+/TX11+/TX21+/TXC1+/- 5 User Guide -- EP9134_UG V0.2 2.2 Pin Diagram Figure 2-2 Pin Diagram AVSS EXT_SWING23 PVDD PVDD PVSS PVSS AVSS AVSS TX23+ TX23AVDD AVDD TX13+ TX13AVSS AVSS TX03+ TX03AVDD AVDD TXC3+ TXC3AVSS AVSS _AVSS _AVSS 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 www..com AVSS TXC2TXC2+ AVDD TX02TX02+ AVSS AVSS TX12TX12+ AVDD TX22TX22+ AVSS AVSS VDD18 VDD18 VSS VSS A0 A1 A2 EXT_RSTb VDD18 VSS SCL1 SDA1 SCL2 SDA2 VDDE VSSE reserved reserved SCL3 SDA3 V_OUT HTPLG0 HTPLG1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 _AVSS _AVSS _AVSS _AVSS _AVSS AVSS RX2+ RX2AVDD RX1+ RX1AVSS AVDD AVSS RX0+ RX0AVSS RXC+ RXCAVDD EXT_RES PVDD PVSS AVSS AVSS TX20+ TX20AVDD TX10+ TX10AVSS AVSS TX00+ TX00AVDD TXC0+ TXC0AVSS 6 HTPLG2 HTPLG3 VDD18 VDD18 VSS VSS AVSS AVSS TXC1TXC1+ AVDD TX01TX01+ AVSS AVSS TX11TX11+ AVDD TX21TX21+ AVSS AVSS PVSS PVDD EXT_SWING01 AVSS Explore Confidential Proprietary NON-DISCLOSURE AGREEMENT REQUIRED User Guide -- EP9134_UG V0.2 2.3 Pin Description Unless otherwise stated, unused input pins must be tied to ground, and unused output pins left open. Table 2-1 IIC Pins NAME SCL1 SDA1 SCL2 SDA2 www..com IN / OUT IN IO OUT IO IN IO IN DESCRIPTION IIC SCL signal for receiver port DDC IIC SDA signal for receiver port DDC (open drain) IIC SCL signal for EE interface (open drain) IIC SDA signal for EE interface (open drain) IIC SCL signal for internal registers access IIC SDA signal for internal registers access (open drain) Determine the lowest 3-bit of the IIC addrress for IIC Port 3 (SCL3/SDA3) SCL3 SDA3 A2, A1, A0 Table 2-2 Misc. Pins NAME EXT_RSTb V_OUT reserved IN / OUT IN OUT IN DESCRIPTION External Reset (Active LOW). A HIGH level indicates normal operation and a LOW level causes all the logic on the chip to be reset. Polarity corrected vertical sync pulse (active high) derived from receiver input Must be tied LOW for normal operation. Table 2-3 Receiver Pins NAME RX0RX0+ RX1RX1+ RX2RX2+ RXCRXC+ EXT_RES Analog IN / OUT DESCRIPTION Differential Data Input Pairs for receiver port Analog Differential Clock Input Pairs for receiver port DVI/HDMI External Termination Resistor Table 2-4 Transmitter Pins NAME TX00TX00+ TX10TX10+ TX20TX20+ TXC0TXC0+ HTPLG0 IN IN / OUT DESCRIPTION Differential Data Output Pairs for transmitter port 0 Analog Differential Clock Output Pairs for transmitter port 0 Hot Plug Input This pin is used to monitor the "HOT PLUG" signal for tansmitter port 0. Note: This input is only 3.3V tolerant and has no internal debouncer circuit. Explore Confidential Proprietary NON-DISCLOSURE AGREEMENT REQUIRED 7 User Guide -- EP9134_UG V0.2 Table 2-4 Transmitter Pins NAME TX01TX01+ TX11TX11+ TX21TX21+ TXC1TXC1+ HTPLG1 www..com IN / OUT DESCRIPTION Differential Data Output Pairs for transmitter port 1 Analog Differential Clock Output Pairs for transmitter port 1 IN Hot Plug Input This pin is used to monitor the "HOT PLUG" signal for tansmitter port 1. Note: This input is only 3.3V tolerant and has no internal debouncer circuit. Voltage Swing Adjust for Port 0/1. A resistor should tie this pin to AVCC. This resistance determines the amplitude of the voltage swing. 560 is recommended. EXT_SWING01 TX02TX02+ TX12TX12+ TX22TX22+ TXC2TXC2+ HTPLG2 TX03TX03+ TX13TX13+ TX23TX23+ TXC3TXC3+ HTPLG3 Analog Differential Data Output Pairs for transmitter port 2 Analog Differential Clock Output Pairs for transmitter port 2 IN Hot Plug Input This pin is used to monitor the "HOT PLUG" signal for tansmitter port 2. Note: This input is only 3.3V tolerant and has no internal debouncer circuit. Differential Data Output Pairs for transmitter port 3 Analog Differential Clock Output Pairs for transmitter port 3 IN Hot Plug Input This pin is used to monitor the "HOT PLUG" signal for tansmitter port 3. Note: This input is only 3.3V tolerant and has no internal debouncer circuit. Voltage Swing Adjust for Port 2/3. A resistor should tie this pin to AVCC. This resistance determines the amplitude of the voltage swing. 560 is recommended. EXT_SWING23 Analog Table 2-5 Power and Ground Pins NAME VDDE VSSE VDD18 VSS AVDD AVSS PVDD IN / OUT PWR GND PWR GND PWR GND PWR Digital Power, 3.3V Digital Ground Core Power, 1.8V Core Ground Analog Power, 3.3V Analog Ground Analog Power for PLL, 3.3V DESCRIPTION 8 Explore Confidential Proprietary NON-DISCLOSURE AGREEMENT REQUIRED User Guide -- EP9134_UG V0.2 Table 2-5 Power and Ground Pins NAME PVSS _AVSS IN / OUT GND GND Analog Ground for PLL Analog Ground DESCRIPTION www..com Explore Confidential Proprietary NON-DISCLOSURE AGREEMENT REQUIRED 9 User Guide -- EP9134_UG V0.2 2.4 Electrical Characteristics Absolute Maximum Conditions Symbol Vcc33 Vcc18 VI VO www..com Parameter 3.3V Supply Voltage 1.8V Supply Voltage Input Voltage Output Voltage Ambient Temperature (with power applied) Storage Temperature Thermal Resistance (Junction to Ambient) Package Power Dissipation Min -0.3 -0.3 -0.3 -0.3 -25 -40 Typ Max 4.0 2.5 Vcc + 0.3 Vcc + 0.3 75 125 Units V V V V TA TSTG C C C/W JA PPD 29.1 2.4 W 1 Permanent device damage may occur if absolute maximum conditions are exceeded. 2 Functional operation should be restricted to the conditions described under Normal Operating Conditions. Normal Operating Conditions Symbol Vcc33 Vcc18 VCCN TA Parameter 3.3V Supply Voltage 1.8V Supply Voltage Supply Voltage Noise1 Ambient Temperature (with power applied) Min 3.14 1.71 -0.3 0 25 Typ 3.3 1.8 Max 3.6 1.98 100 70 Units V V mVp-p C 1 Guaranteed by design. DC Digital I/O Specifications (under normal operating conditions unless otherwise specified) Symbol VIH VIL VOH Parameter High-level Input Voltage Low-level Input Voltage High-level Output Voltage 2.4 Conditions Min 2.0 0.8 Typ Max Units V V V 10 Explore Confidential Proprietary NON-DISCLOSURE AGREEMENT REQUIRED User Guide -- EP9134_UG V0.2 VOL IOL VID Low-level Output Voltage Output Leakage Current Differential Input Voltage, Single Ended Amplitude High Impedance -10 150 0.4 10 1000 V uA mV DC Analogue Specifications (under normal operating conditions unless otherwise specified) Symbol www..com VOD Parameter Differential Voltage Single ended peak to peak amplitude Differential High-level Output Voltage1 Differential Output Short Circuit Current Power-Down Current2 Conditions RLOAD = 50 ohm REXT_SWING = 430 ohm Min 510 Typ 550 AVCC Max 590 Units mV mV VDOH IDOS IPD VOUT = 0V 3V3 25C Ambient 1V8 3V3 1080p Resolution (8-bit) 1V8 1 2 5 V mA mA 440 110 449 110 484 164 mA mA mA mA mA mA ICCD Supply Current (25C Ambient, REXT_SWING = 430 ohm, 3V3 UXGA Resolution (8-bit) 1V8 3V3 1080p Resolution (12-bit) 1V8 TX0/TX1/TX2/TX3 are Active) 1 Guaranteed by design. 2 Assumes all HDMI/DVI I/O ports are not connected and all digital inputs are scilent. Receiver AC Specifications (under normal operating conditions unless otherwise specified) Symbol TDPS TCCS TIJIT TPDL THSC TFSC Parameter Intra-Pair (+ to -) Differential Input Skew1 Channel to Channel Differential Input Skew1 Differential Input Clock Jitter Tolerance2,3 Delay from OUT_EN Low to High Impedance outputs Link Disabled (Tx power down) to LINK_ON Low4 Link Enabled (DE Active) to LINK_ON High1 25 Conditions Min Typ Max 0.4 1.0 0.3 10 250 40 Units Tbit Tpixel Tbit ns ms DE edges Explore Confidential Proprietary NON-DISCLOSURE AGREEMENT REQUIRED 11 User Guide -- EP9134_UG V0.2 NOTES: 1. Guaranteed by design. 2. Jitter defines as per DVI 1.0 Specification, Section 4.6 Jitter Specification. 3. Jitter measured with Clock Recovery Unit as per DVI 1.0 Specification, Section 4.7 Electronical Measurement Procedures 4. Measured when transmitter was powered down. Transmitter AC Specifications (under normal operating conditions unless otherwise specified) Symbol SLHT Parameter Differential Swing Low-to-High Transition Time Conditions CLOAD = 5pF, RLOAD = 50 ohm, REXT_SWING = 300 ohm CLOAD = 5pF, RLOAD = 50 ohm, REXT_SWING = 300 ohm Min 170 Typ 200 Max 230 Units ps www..com SHLT Differential Swing High-to-Low Transition Time 170 200 230 ps 2 Jitter can be estimated by 1) triggering a digital scope at the rising of input clock and 2) measuring the peak to peak time spread of the rising edge of the input clock at both 0.5us and 1.0us after the trigger. 3 Actual jitter tolerance may be higher depending on the frequency of the jitter. Figure 2-3 Differential Output Timing Definition AVCC 50ohm VOD = ABS{(TX+) - (TX-)} TX+ TX- 80% VOD 20% VOD 5pF SLHT SHLT 12 Explore Confidential Proprietary NON-DISCLOSURE AGREEMENT REQUIRED User Guide -- EP9134_UG V0.2 Section 3 Detail Functional Descriptions 3.1 General The chip provides an IIC (SCL3/SDA3) serial bus interface to communicate with the host. The IIC address for this slave IIC interface is "0111_A2_A1_A1_x" (where x=1 for read and x=0 for write). A2, A1 and A0 are programmable by pins 3.2 IIC Interface www..com The IIC bus interface uses a Serial Data line (SDA at pin SDA3) and a Serial Clock Line (SCL at pin SCL3) for data transfer. The chip acts as a slave for receiving and transmitting data over the serial interface. All devices connected to the IIC bus must have open drain or open collector outputs. Logic AND function is exercised on both lines with external pull-up resistors, the value of these resistors is system dependent. When the serial interface is not active, the logic levels on SCL and SDA are pulled HIGH by external pull-up resistors. Data received or transmitted on the SDA line must be stable at the positive edge of SCL. If the SDA changes state while SCL is HIGH, the IIC interface interprets that action as a START or STOP sequence. Data on SDA must change only when SCL is LOW. The standard IIC traffic protocol is illustrated in the following Figure: Figure 3-1 IIC Bus Transmission Protocol MSB SCL 1 2 3 4 5 6 7 LSB 8 9 MSB 1 2 3 4 5 6 7 LSB 8 9 SDA AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W XXX D7 D6 D5 D4 D3 D2 D1 D0 Start Signal Calling Address Read/ Ack Write Bit Data Byte No Stop Ack Signal Bit LSB MSB SCL 1 2 3 4 5 6 7 LSB 8 9 MSB 1 2 3 4 5 6 7 8 9 SDA AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W XX AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W Start Signal Calling Address Read/ Ack Write Bit Repeated Start Signal New Calling Address Read/ No Stop Write Ack Signal Bit Explore Confidential Proprietary NON-DISCLOSURE AGREEMENT REQUIRED 13 User Guide -- EP9134_UG V0.2 3.2.1 Basic Protocol For EP9122, there are six components to serial bus operation: * * * * * START Signal Slave Address Byte Base Register Address Byte Data Byte for Read/Write STOP Signal When the serial interface is inactive (SCL and SDA are HIGH), communication are initiated by a START signal www..comwhich is a HIGH-to-LOW transition on SDA while SCL is HIGH. The first eight bits of data transferred after a START signal comprising a seven bit slave address (the seven MSB bits) and a single R/W bit (the LSB bit). The R/W bit indicates the direction of data transfer, "1" means read from device and "0" means write to device. If the transmitted slave address matches the address of the device, the EP9122 sends the acknowledge by asserting SDA Low on the ninth SCL pulse. Else, the EP9122 does not assert the acknowledge. Writing data to specific control registers of the chip requires that the 8-bits address of the control register is written after the slave address has been acknowledged. This control register address is the base address for the subsequent write operations. The base address auto-increments by one for each byte of data written after the data byte intended for the base address. The acknowledge bit will be sent on the ninth SCL pulse after every 8-bits data received. Data are read from the control registers of the chip in a similar manner. Reading requires two data transfer operations: The base address must be written with the R/W bit of the slave address byte LOW to set up a sequential read operation. Reading (the R/W bit of the slave address byte HIGH) begins at the previously established base address. The address of the read register auto-increments after each byte is transferred. To terminate a read/write sequence to the chip, a STOP signal must be sent. A STOP signal comprises a LOW-to-HIGH transition of SDA while SCL is HIGH. A repeated start signal occurs when the master device driving the serial interface generates a START signal without first generating a STOP signal to terminate the current read/write sequence. This can be used to change the mode of communication (read, write) between the slave and master without releasing the bus. 3.2.2 Examples of the read/write sequence Write to One Control Register * * * START Signal Slave Address Byte (R/W bit = LOW) Base Address Byte 14 Explore Confidential Proprietary NON-DISCLOSURE AGREEMENT REQUIRED User Guide -- EP9134_UG V0.2 * * Data Byte to Base Address STOP Signal Write to Multiple Control Registers * * * * * www..com START Signal Slave Address Byte (R/W bit = LOW) Base Address Byte Data Byte to Base Address Data Byte to (Base Address + 1) Data Byte to (Base Address + 2) ................................................... Data Byte to (Base Address + N) STOP Signal * * * * Read from One Control Register * * * * * * * * START Signal Slave Address Byte (R/W bit = LOW) Base Address Byte STOP Signal (Optional) START Signal Slave Address Byte (R/W = HIGH) Data Byte from Base Address STOP Signal Read from Multiple Control Registers * * * * * * * * * * START Signal Slave Address Byte (R/W bit = LOW) Base Address Byte STOP Signal (Optional) START Signal Slave Address Byte (R/W = HIGH) Data Byte from Base Address Data Byte from (Base Address + 1) Data Byte from (Base Address + 2) ....................................................... Explore Confidential Proprietary NON-DISCLOSURE AGREEMENT REQUIRED 15 User Guide -- EP9134_UG V0.2 * * Data Byte from (Base Address + N) STOP Signal 3.3 Description of the Control Registers The following table shows all the control registers of the DVI/HDMI Transmitter EP9134: Table 3-1 IIC Control Registers Addr $05 www..com Mode R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R Bit7 - Bit6 - Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 RESET 04h 00h TMDS_SAMP[5:0] TMDS_CTL1[7:0] $06 $07 $08 $09 $0A $0E $0F $10 $11 $12 $13 $14 $15 $16 $17 $18 $19 $1A $1B $1C $1D $1E $1F RX_LINK_ON RX_DE_ON RX_VSYNC RX_HDMI - RX_ENC_ON RX_PU - TX_RSEN - TX_SEL[1:0] TX_ENC_OPT 08h 01h 00h 80h 01h 00h XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh TX_MUTE - - TX_PU TX_HDMI TX_ENC_EN - TX_HTPLG RESERVED[3:0] TX_AKSV_RDY TX_EESS TX_RI_RDY TX_ENC_ON - TX_RPTR - TX_BKSV_1 TX_BKSV_2 TX_BKSV_3 TX_BKSV_4 TX_BKSV_5 TX_AN_1 TX_AN_2 TX_AN_3 TX_AN_4 TX_AN_5 TX_AN_6 TX_AN_7 TX_AN_8 TX_AKSV_1 TX_AKSV_2 TX_AKSV_3 16 Explore Confidential Proprietary NON-DISCLOSURE AGREEMENT REQUIRED User Guide -- EP9134_UG V0.2 $20 $21 $22 $23 R R R R TX_AKSV_4 TX_AKSV_5 TX_RI_1 TX_RI_2 XXh XXh XXh XXh 3.3.1 Register Descriptions Detailed usage of these IIC registers is described in the following section. www..com 3.3.1.1 TMDS Control Register 0 Table 3-2 TMDS Control Register 0 $05 7 R W Reset: 0 6 0 5 4 3 2 1 0 TMDS_SAMP[5:0] 0 0 0 0 0 1 0 0 TMDS_SAMP[5:0] -- TMDS Sampling Logic Control Parameters This register has to be programmed with the value 0x08 after the power on sequence if the expected supported TMDS clock frequency is up to 225MHz (1080p, 12 bits deep color). 3.3.1.2 TMDS Control Register 1 Table 3-3 TMDS Control Register 1 $06 7 R W Reset: 6 5 4 3 2 1 0 TMDS_CTL1[7:0] 0 0 0 0 0 0 0 0 TMDS_CTL1[7:0] -- TMDS Control Register 1 This register has to be programmed with the value 0xA2 after the power on sequence if the expected supported TMDS clock frequency is up to 225MHz (1080p, 12 bits deep color). Explore Confidential Proprietary NON-DISCLOSURE AGREEMENT REQUIRED 17 User Guide -- EP9134_UG V0.2 3.3.1.3 Control Register 0 Table 3-4 Control Register 0 $07 7 R RX_LINK_ON W Reset: 6 RX_DE_ON - 5 RX_HDMI - 4 RX_ENC_ON - 3 RX_PU 2 - 1 TX_SEL[1:0] 0 - - - 1 0 0 0 RX_LINK_ON -- Receiver Link On This bit indicates whether a valid signal appears at the clock input of the receiver port. This bit is valid even when the receiver is powered off. www..com 1 = Clock presents at the input of the receiver port 0 = No clock is detected at the input of the receiver port RX_DE_ON -- Receiver DE On This bit indicates whether DE signal is toggling at the receiver port. This bit is valid only when the receiver is powered on. 1 = DE signal is toggling at the receiver port 0 = DE signal is not toggling at the receiver port RX_HDMI -- Receiver HDMI signal This bit indicates whether the receiver port is receiving DVI or HDMI signal 1 = HDMI 0 = DVI RX_ENC_ON -- Receiver Decryption On This bit indicates whether the HDCP decryption is active at the receiver port. 1 = HDCP decryption at the receiver port is active 0 = HDCP decryption at the receiver port is not active RX_PU -- Receiver Power Down Control Bit This bit controls the power of the receiver port 1 = Normal operation. 0 = Power down Mode. TX_SEL[1:0] -- Transmitter Port Select for IIC Access The 4 transmitter ports share the same IIC register address. This register is used to select which transmitter port is addressed for IIC access. 00 = Port 0 is selected 01 = Port 1 is selected 10 = Port 2 is selected 11 = Port 3 is selected 18 Explore Confidential Proprietary NON-DISCLOSURE AGREEMENT REQUIRED User Guide -- EP9134_UG V0.2 3.3.1.4 Control Register 1 Table 3-5 Control Register 1 $08 7 R W Reset: TX_MUTE 6 RX_VSYNC - 5 - 4 - 3 - 2 - 1 TX_ENC_OPT 0 TX_PU 0 - - 0 - - 0 1 TX_MUTE -- Video Mute Transmitter The bit is used to mute the video for the selected transmitter port. 1 = Selected transmitter port is video muted www..com 0 = Normal VSYNC -- Vertical Sync Status Bit The VSYNC bit gives the current status of the vertical sync signal received by the receiver. TX_ENC_OPT -- Transmitter Encryption Option 1 = Not affected by RX encryption status. 0 = Force not to encrypt if RX is not encrypted. TX_PU -- Transmitter Power Down Control Bit This bit controls the power of the selected transmitter port 1 = Normal operation. 0 = Put the selected transmitter port in power down mode. 3.3.1.5 Control Register 2 Table 3-6 Control Register 2 $09 7 R W Reset: 6 5 4 3 2 TX_RSEN 1 TX_HTPLG - 0 - - - - - - - - - TX_RSEN -- Transmitter Analog Output Status Bit The TX_RSEN bit indicates the analog output status at the selected transmitter port. 1 = The selected transmitter analog outputs are connected to the receiver 0 = The selected transmitter analog outputs are disconnected TX_HTPLG -- Transmitter Hot Plug Status Bit The TX_HTPLG bit indicates the hot plug status at the selected transmitter port. 1 = Hot Plug detected at the selected transmitter port. 0 = Hot Plug not detected at the selected transmitter port. Explore Confidential Proprietary NON-DISCLOSURE AGREEMENT REQUIRED 19 User Guide -- EP9134_UG V0.2 3.3.1.6 Control Register 3 Table 3-7 Control Register 3 $0A 7 R W Reset: 6 5 4 3 2 1 0 RESERVED[3:0] 1 0 0 0 - - - - RESERVED[3:0] -- RESERVED Control Bits Set www..com the reserved registers to 0x80 as the default value. 3.3.1.7 Control Register 4 Table 3-8 Control Register 4 $0E 7 R W Reset: 6 5 4 3 2 1 TX_EESS 0 TX_HDMI - - - - - - 0 1 TX_EESS -- Enable Enhanced Encryption Signalling for the selected transmitter port 1 = Using Enhanced Encryption Signalling for the selected transmitter port. 0 = Using Original Encryption Signalling for the selected transmitter port. This is only valid if the selected transmitter is working in DVI mode (TX_HDMI = 0). TX_HDMI -- Set HDMI mode for the selected transmitter port 1 = Put the selected transmitter port working in HDMI mode. This is valid only if the receiver is receiving HDMI signal. 0 = Put the selected transmitter port working in DVI mode. 3.3.1.8 Control Register 5 Table 3-9 Control Register 5 $0F 7 6 R TX_AKSV_RDY TX_ENC_ON W Reset: 5 4 TX_RPTR 3 2 1 TX_RI_RDY 0 TX_ENC_EN - 0 - - - 0 TX_AKSV_RDY -- Transmitter AKSV Ready The TX_AKSV_RDY bit indicates whether the HDCP keys and AKSV has been successfully downloaded from external EE or not for the selected transmitter port. This bit is read only. 20 Explore Confidential Proprietary NON-DISCLOSURE AGREEMENT REQUIRED User Guide -- EP9134_UG V0.2 1 = HDCP keys and AKSV has been successfully downloaded from external EE. AKSV is ready for read. 0 = HDCP keys and AKSV downloading has not been completed. AKSV is not ready for read. TX_ENC_ON -- Transmitter HDCP Encryption On The TX_ENC_ON bit indicates whether the HDCP encryption for the selected transmitter port is active or not. This bit is read only. 1 = HDCP encryption is active. 0 = HDCP encryption is not active. TX_RPTR -- Transmit to Repeater The TX_RPTR bit should be set if the receiver side which is connected to the selected transmitter port is a www..com repeater. It should be cleared otherwise. 1 = The selected transmitter port is connecting to a repeater. 0 = The selected transmitter port is not connecting to a repeater. TX_RI_RDY -- Transmitter RI Ready This bit indicates that the first Ri value is available for the selected transmitter port. This bit is read only. 1 = First Ri value is available for the selected transmitter port. 0 = First Ri value is not available for the selected transmitter port. TX_ENC_EN -- Transmitter ENC Enable 1 = Enable HDCP encryption for the selected transmitter port. 0 = Disable HDCP encryption the selected transmitter port. 3.3.1.9 TX_BKSV Registers ($10 ~ $14) - TX_BKSV_1 ~ TX_BKSV_5 Table 3-10 TX_BKSV Registers $10 ~ $14 bit R W Reset: 7 6 5 4 3 2 1 0 TX_BKSV1[7:0] ~ TX_BKSV5[7:0] - These 5 registers for the selected transmitter port should be programmed with receiver's Key Selection Vector. TX_BKSV_1 is the LSB and TX_BKSV_5 is the MSB. TX_BKSV_5 should be written last, as it triggers the authentication process. Explore Confidential Proprietary NON-DISCLOSURE AGREEMENT REQUIRED 21 User Guide -- EP9134_UG V0.2 3.3.1.10 TX_AN Registers ($15 ~ $1C) - TX_AN_1 ~ TX_AN_8 Table 3-11 TX_AN Registers $15 ~ $1C bit R W Reset: 7 6 5 4 3 2 1 0 TX_AN1[7:0] ~ TX_AN8[7:0] - These 8 registers for the selected transmitter port should be programmed with a 64-bit pseudo-random value before triggering the authentication process. TX_AN_1 is the LSB and TX_AN_8 is the MSB. www..com 3.3.1.11 TX_AKSV Registers ($1D ~ $21) - TX_AKSV_1 ~ TX_AKSV_5 Table 3-12 TX_AKSV Registers $1D ~ $21 bit R W Reset: 7 6 5 4 3 2 1 0 TX_AKSV1[7:0] ~ TX_AKSV5[7:0] - These 5 registers are read only which hold transmitter's Key Selection Vector for the selected transmitter port. TX_AKSV_1 is the LSB and TX_AKSV_5 is the MSB. All five bytes should be read from here and then written to the receiver. Byte 5 should be written last to the receiver, as it will trigger authentication there. These 5 registers should not be read until TX_AKSV_RDY bit is 1. 3.3.1.12 TX_RI Registers ($22 ~ $23) - TX_RI_1 ~ TX_RI_2 Table 3-13 TX_RI Registers $22 ~ $23 bit R W Reset: 7 6 5 4 3 2 1 0 TX_RI_1[7:0] ~ TX_RI_2[7:0] - These 2 registers hold transmitter's Ri value for the selected transmitter port. They should be read and compared against the Ri value of the receiver to ensure that the encryption process on the transmitter and receiver is synchronized. 22 Explore Confidential Proprietary NON-DISCLOSURE AGREEMENT REQUIRED User Guide -- EP9134_UG V0.2 Section 4 Package 128 Pin HQFP 64 14.0 TYP 39 38 20.0 TYP 23.2 TYP 2.8 TYP 3.4 MAX 0.20 TYP 17.2 TYP www..com EP9134 date code lot number 128 1 0.5 TYP UNITS: mm Explore Microelectronics NON-DISCLOSURE AGREEMENT REQUIRED 23 User Guide -- EP9134_UG V0.2 www..com 24 Explore Microelectronics NON-DISCLOSURE AGREEMENT REQUIRED User Guide -- EP9134_UG V0.2 User Guide End Sheet www..com Explore Confidential Proprietary NON-DISCLOSURE AGREEMENT REQUIRED 25 User Guide -- EP9134_UG V0.2 www..com FINAL PAGE OF 26 PAGES 26 Explore Confidential Proprietary NON-DISCLOSURE AGREEMENT REQUIRED |
Price & Availability of EP9134
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |